In recent years, as a wiring substrate for use in a semiconductor device, a substrate having a multi-layer structure has been extensively used. The wiring substrate having the multi-layer structure is, for example, formed by stacking a plurality of wiring layers on a silicon substrate. In the wiring substrate, the wiring layers are stacked with insulating layers interposed every therebetween and are electrically connected to one other via electrode layers. An example of such a wiring substrate is a relay substrate called an interposer. The interposer, for example, is installed between a semiconductor element and a packaging substrate to electrically connect the semiconductor element to the packaging substrate.
FIG. 15 is a sectional view illustrating the structure of an interposer according to a related art. As illustrated in FIG. 15, for example, the interposer is formed using a silicon substrate 10 as a base. The interposer has a wiring pattern 11 on a surface and a wiring pattern 12 on the other surface. The wiring pattern 11 and the wiring pattern 12 are electrically connected to each other via a through electrode 14 formed in a through hole 13 passing through the silicon substrate 10. An oxide layer 15 serving as an insulating layer is formed on the outer surface of the silicon substrate 10 and the inner wall surface of the through hole 13. In addition, the surfaces of the wiring pattern 11 and the wiring pattern 12, for example, are coated with an insulating layer 16 made of polyimide.
In the wiring substrate having the multi-layer structure as described above, there is a situation in which an adhesive layer is formed between a wiring layer and an insulating layer or between a wiring layer and an electrode layer to improve the adhesion property between the layers. For example, in the interposer illustrated in FIG. 15, a titanium (Ti) layer 17 as an adhesive layer is formed between the wiring pattern 11 and the through electrode 14 and between the wiring pattern 11 and the oxide layer 15. Furthermore, a copper layer 18 is formed between the wiring pattern 11 and the titanium layer 17 as an underlayer of the wiring pattern 11. In addition, in the same manner, a titanium layer and a copper layer are also formed between the wiring pattern 12 and the through electrode 14 and between the wiring pattern 12 and the oxide layer 15.
The interposer, for example, is formed through a manufacturing method described below. FIGS. 16A to 16F are diagrams illustrating an example of a manufacturing method of an interposer according to a related art. FIGS. 16A to 16F illustrate the sections of the interposer in respective steps. First, as illustrated in FIG. 16A, thermal oxidation is performed to form an oxide layer 15 on the outer surface of a silicon substrate 10 and the inner wall surface of a through hole 13 formed in the silicon substrate 10. Then, a through electrode 14 is formed in the through hole 13.
As illustrated in FIG. 16B, a titanium layer 17 is formed on a surface of the silicon substrate 10 through sputtering. The titanium layer 17 serves as an adhesive layer between a wiring pattern 11 and the through electrode 14 and between the wiring pattern 11 and an oxide layer 15. Then, a copper layer 18 is formed on the titanium layer 17 through sputtering as an underlayer of the wiring pattern 11. As illustrated in FIG. 16C, a resist pattern 19 is formed on the copper layer 18. For example, the resist pattern 19 is formed by applying photoresist to the surface of the copper layer 18 and then exposing and developing the photoresist using a photomask.
As illustrated in FIG. 16D, the wiring pattern 11 is formed on the copper layer 18 through electrolytic copper plating. After the formation of the wiring pattern 11, the resist pattern 19 is stripped as illustrated in FIG. 16E. Next, as illustrated in FIG. 16F, etching is performed to remove the titanium layer 17 and the copper layer 18 located at places where the resist pattern 19 has been stripped off.
Through the manufacturing process as described above, the interposer comes to have the titanium layer 17 as an adhesive layer between the wiring pattern 11 and the through electrode 14 and between the wiring pattern 11 and the oxide layer 15. Furthermore, through the same process, the titanium layer as an adhesive layer is also formed between the wiring pattern 12, which is formed on the other surface of the silicon substrate 10, and the through electrode 14, and between the wiring pattern 12 and the oxide layer 15.    Patent Document 1: Japanese Laid-open Patent Publication No. 2009-277895.